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E20-385 - E20-385 Data Domain Specialist for Implementation Engineers - BrainDump Information

Vendor Name : EMC
Exam Code : E20-385
Exam Name : E20-385 Data Domain Specialist for Implementation Engineers
Questions and Answers : 207 Q & A
Updated On : March 18, 2019
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E20-385 exam Dumps Source : E20-385 Data Domain Specialist for Implementation Engineers

Test Code : E20-385
Test Name : E20-385 Data Domain Specialist for Implementation Engineers
Vendor Name : EMC
Q&A : 207 Real Questions

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EMC E20-385 Data Domain Specialist

EMC/information domain/NetApp and facts deduplication: exclusive news insurance and evaluation | killexams.com Real Questions and Pass4sure dumps

EMC Corp. and NetApp battled for six weeks over facts area Inc., a number one enterprise in data deduplication technology. NetApp positioned an customary offer on statistics area for $1.5 billion on may additionally 20. quickly after, EMC challenged that bid, and the two businesses went back and forth in their offers for a couple of weeks, except July 6, when EMC placed the highest bid of $2.1 billion. NetApp stepped down from the bidding warfare on July 8, and records domain approved EMC's present of $2.1 billion. we have now compiled our full coverage of the EMC/statistics domain/NetApp battle, expert guidance, podcast interviews, and our foremost supplies on records deduplication.

EMC/records domain/NetApp: table of contents

EMC/data domain/NetApp news coverageEMC/statistics domain/NetApp podcasts information deduplication technology substances

 

EMC/statistics domain/NETAPP exclusive information insurance

EMC acquires records area for $2.1B after NetApp drops bidEMC wins the combat over data domain. NetApp pointed out it will no longer boost its bid to purchase the facts deduplication backups specialist, and facts domain's board authorized the $2.1 billion offer EMC made July 6 and entered right into a definitive agreement.

EMC raises its acquisition offer for information deduplication vendor information area to $2.1BEMC raised the stakes in its bidding battle for statistics deduplication backup professional information area Inc., increasing its all money offer to $33.50 per share or $2.1 billion in an attempt to sway the information area board from accepting NetApp's present of $1.9 billion.

Storage trade weighs EMC's, NetApp's bidding warfare for facts DomainStorage directors maintain an in depth eye on EMC's and NetApp's bidding struggle for statistics area Inc. after NetApp raises the bid to $1.9 billion, and wonder how the destiny of the information deduplication backup specialist will have an impact on the storage business.

EMC wants to purchase statistics area for $1.eight billion to dominate data deduplication marketEMC provided $1.eight billion to purchase information area, eclipsing NetApp's $1.5 billion present for the target-based mostly deduplication backup specialist on may also 20.

NetApp plans to purchase statistics deduplication professional facts area for $1.5 billionNetApp Inc. made a daring move to develop into the market chief in facts deduplication technology when it obtained statistics domain Inc. for $1.5 billion in a blended cash and inventory transaction.

PODCASTS ON EMC/NETAPP/records domain: professional OPINION AND analysis 

EMC continues the battle for information area with new bid of $2.1 billionThe bidding battle between EMC and NetApp over statistics area persisted as EMC raised the bid to a great money offer of $2.1 billion. Beth Pariseau, senior news writer at SearchStorage.com, and Curtis Preston, government editor at TechTarget, talk about the latest traits of the story during this podcast.

EMC and NetApp proceed the battle over information DomainEMC raised the bid to $1.eight billion. Beth Pariseau, senior information author for SearchStorage.com, talks in regards to the merits of having statistics domain in a company, and what this deal may mean for the longer term. And Curtis Preston, government editor at TechTarget and impartial backup professional, talks about the battle between EMC and NetApp.

records DEDUPLICATION substances: OUR properly five facts DEDUPE suggestions 

statistics deduplication can keep organizations time and cash by means of enabling extra information healing from disk and cutting back the footprint and vigour and cooling requirements of secondary storage. be mindful where and how to use statistics deduplication know-how in disk-based mostly backup listed here.

if you've decided that your information backup device can benefit from data deduplication, you really have a variety of choices. during this tutorial, we examine publish-processing versus inline deduplication, disk-based mostly backup and dedupe, and compare the well-known deduplication products. be trained every little thing you should know about deduplication in our statistics deduplication tutorial.

statistics deduplication is one of the hottest technologies in data backup and healing. however before you put into effect a deduplication product, you'll want to trust even if it gives world deduplication. be taught why global deduplication is critical in this tip.

statistics deduplication ratios may also be very complicated. find out about how to estimate a data deduplication ratio on your backup equipment and the way to consider a dedupe product. you will also be trained what's a practical data dedupe ratio to are expecting from a backup product listed here.

statistics deduplication is longer a bleeding-part know-how, and the cost mark downs of statistics reduction is chiefly attractive as agencies contend with information boom and tightening budgets. SearchDataBackup.com requested clients concerning the deduplication products they've deployed, and the professionals and cons of every. study information deduplication approached in backup nowadays.


red Hat acquires records cleansing professional Permabit’s know-how & property | killexams.com Real Questions and Pass4sure dumps

crimson Hat Inc. is bolstering its storage product portfolio with the acquisition of Permabit expertise Corp.’s know-how belongings, the commercial enterprise Linux company revealed Monday.

The settlement will additionally see sixteen of Permabit’s employees join purple Hat. terms of the deal were now not disclosed.

centered returned in 2000 with a total of $12 million in task capital funding behind it, Permabit has through the years managed to carve out a gap for itself as a professional in what it calls “information effectivity expertise.” extra especially, it presents items that allow agencies to clear up their company data a good way to access it quicker and save it greater efficaciously. It also sells statistics compression technology. in addition, the enterprise has partnered with pink Hat considering the fact that 2016 to be sure its utility works with the latter’s storage items.

In a statement, crimson Hat noted the addition of Permabit’s statistics deduplication and compression applied sciences should be a fine fit for its personal storage offerings. “With the addition of Permabit’s statistics deduplication and compression tools to pink Hat business Linux, purple Hat could be ready to aid these companies as they are searching for to derive a greater effective storage footprint,” noted Jim Totton, a red Hat vice chairman and accepted manager.

The acquisition should as a minimum make crimson Hat’s storage products greater appealing. information storage is cheap however it nonetheless comes at a cost, and people fees do add up for companies transitioning to greater expensive but more suitable-performing flash storage. This same common sense become additionally pointed out to be the incentive at the back of EMC Corp.’s $2.four billion acquisition of statistics domain Corp., yet another enterprise that cleans records, again in 2009.

crimson Hat observed the deal will “have no fabric have an impact on” on its 2nd-quarter or fiscal-yr profits.

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Rackspace Joins EMC velocity carrier provider companion software | killexams.com Real Questions and Pass4sure dumps

SAN ANTONIO--(enterprise WIRE)--Rackspace® internet hosting (NYSE: RAX), the provider chief in cloud computing, today announced it will extend its relationship with EMC through joining the EMC velocity™ carrier company software to boost new cloud-primarily based carrier offerings. the two groups have collaborated given that 2001 to carry a full latitude of resourceful options leveraging EMC’s portfolio of counsel infrastructure items including digital storage and various cloud-based information administration services.

“Our conclusion-clients will advantage from the relationship between EMC and Rackspace as it offers the IT options from both agencies on one seamless offering while decreasing charges,” noted Jim Lewandowski, senior vp of global income for Rackspace. “during the past, meeting computing needs intended you needed to buy servers, appoint technical ability after which constantly reinvest to sustain with expertise. Now the end-clients can shift their center of attention to their mission-crucial apps, core expertise and innovation whereas being supported with the aid of our hallmark Fanatical assist.”

With the improved relationship the agencies will work collectively on new, joint solutions in order to enable agencies to optimize efficiencies and reduce expenses. throughout the speed service company companion application, EMC will work with Rackspace to permit Rackspace to convey a wide variety of cloud-primarily based IT features to the world IT market.

latest service offerings consist of Rackspace managed commercial enterprise deepest Clouds that are based on EMC Symmetrix VMAX™ and EMC VNX™ unified storage to deliver business storage enviornment networks. moreover, Rackspace provides statistics replication capabilities based on EMC RecoverPoint, EMC information area®, and EMC Isilon® items. Rackspace also presents EMC options with Fanatical guide®, giving end-clients a much wider choice of cloud-primarily based IT options and tactical advantages equivalent to cost reductions, flexibility and scalability coupled with world-classification guide to enhance its efficiency.

“As long time companions, the expansion of our relationship to develop new cloud-based solutions is a herbal evolution. Rackspace’s rock solid basis and world category Fanatical assist mixed with EMC’s portfolio of products that are optimized for digital environments will enable Rackspace to bring inventive cloud computing offerings,” noted EMC’s Dennis Hoffman, Senior vice president, carrier suppliers. “EMC is dedicated to working with carrier providers like Rackspace to convey trusted, enterprise-class cloud features that permit our mutual purchasers to choose the correct source for each IT workload.”

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SPDM: From Extreme Disappointment to the Democratization of Simulation? | killexams.com real questions and Pass4sure dumps

Simulation and analysis (S&A) are not known for its simplicity. It has traditionally been the domain of experts. The problems they encounter are theoretically complex, and the software used reflects this complexity.

Nevertheless, S&A has become a key area of product development. This raises questions like: How can it be made easier? How can we spread the use of these tools to a wider part of the product design community? And, can simulation process and data management (SPDM) help to democratize S&A?

A broader user base. Commercial SPDM solutions are only in use by less than five percent of simulation specialist engineers in mainstream companies. But with easy-to-use apps that contain, among other things, embedded simulation expertise, there is promise of a possible broadening of the user base.

A broader user base. Commercial SPDM solutions are only in use by less than five percent of simulation specialist engineers in mainstream companies. But with easy-to-use apps that contain, among other things, embedded simulation expertise, there is promise of a possible broadening of the user base.

Let us look at simulation with a focus on SPDM. The adoption of SPDM within mainstream product development has, according to CIMdata, “been extremely disappointing from a business impact perspective.”

According to the analyst, fewer than five percent of all simulation specialists worldwide use some form of commercial simulation data management technology to manage and archive their simulation models and to collaborate with other simulation specialists and design disciplines within their organizations. With this in mind, a broader use of simulation tools and results can become powerful support for important advances in the utilization of modern product development technology

Although there are exceptions, simulation software is generally not easy to use, share, or, for that matter, even understand for some members of product development teams. At the same time, the capabilities of the software and the results are necessary to understand the physical behavior of designs and to validate their functionality, strength, motion in a flow, etc., as well as satisfy regulatory requirements. This does not mean that they’re not useful for less complex simulations. But in general, their overall effect has been bottlenecks in the product design process, making for a longer time to market, and a longer wait before revenues start rolling in.

Can the tools and processes become more useful not only for the analysts, but also in the broader "designer collective" in this development chain's increasingly important link?

Process Templates Are Not the Answer Gartner Group's PLM analyst and vice president, Marc Halpern, was one of the first employees ofthe now market-leading CAE software developer ANSYS.

Gartner Group's PLM analyst and vice president, Marc Halpern, was one of the first employees of the now market-leading CAE software developer ANSYS.

Gartner's PLM analyst and vice president, Marc Halpern, has a solid background in simulation and analysis. He was one of the earliest employees in ANSYS, the leading simulation software vendor. There is of course more than one solution to the democratization of simulation software, he notes, but an interesting aspect that is sometimes heard in the discussions is: "Democratize CAE with SPDM (simulationprocess and data management)." But can SPDM really democratize CAE? Both yes and no, says Halpern:

“I have always understood SPDM as a way to manage models and results. A single CAD model can be used to create many different models to perform many different simulations. Although simulation models and data are managed perfectly, this in and of itself does not mean that CAE becomes more democratic. Not even the ‘process templates’ can solve the basic problem,” Halpern claims, pointing to things like general confidence in the results.

“Does the model used match reality so that the results become useful? Another important point is about the interpretation of the results, which can be a problem.”

On the other hand, Halpern says that there are promising examples of embedded expert knowledge and methods in SPDM solutions, pointing at (Aras-owned) Comet’s SimApps. “I believe this is what differentiates what Aras is selling from what I typically see from SPDM technology,” he said.

Though the concept of simulation with good SPDM has been recognized as having a lot of potential, the adoption of SPDM solutions has been an “extreme disappointment", as CIMdata formulates it. 

The emergence of simulation as a key technology can be seen in reduced use of physical prototypes. Simulation and analysis tools can replace a physical prototype with its digital version. Products that only exist virtually must be tested and validated before they are produced. Not only that, in the era of mass individualization, a large number of variations can produce families of products or parts, and they all have to work. 

With a connected product (IoT), the operation of a product will also generate usage data and information about the part’s environment and operating conditions. 

ERP is Immediate ROI, SPDM is Long-Term

As a result of these trends and new technologies, the number of simulations has increased dramatically in the last decade, reflected in the growth of investments in simulation and analysis tools.

According to CIMdata, this growth has made simulation the “star” of the PLM industry, with annual growth rates of around 10 percent over each of the past five years. They have thus also achieved an average growth substantially higher than other PLM investments (CAx, ALM, cPDm etc.) during the same period.

In 2017, investments into simulation software and service investments were worth $5.5 billion, making up 13 percent of the total of the PLM investments.

So, how has this fertile climate affected the growth of SPDM? While CIMdata states "the end-user's interest in SPDM has increased significantly over the past decade," increased interest has not caused increased implementation. CIMdata voices "an extreme disappointment" over the slow industrial uptake of SPDM, at least outside the major automotive and aerospace industry’s OEM companies.

But Halpern is not surprised. “There are good reasons for this [slow uptake]. In stark contrast to ERP investments—which provide immediate cost-saving effects that are directly reflected in the form of profits and rising share prices—SPDM investments are more likely to provide long-term positive effects, which are more difficult to detect immediately. SPDM can make engineers more productive in a way that, from management's point of view, does not have the short-term, immediate benefits that ERP provides,” explains the Gartner analyst. Since so few senior executives understand SPDM, they can’t really support it. SPDM is not like product design, sourcing and manufacturing operations, where what can go wrong can be quite obvious, cause delays in the delivery of the product, and affect the company’s bottom line. 

They know that construction and technology are important, Halpern adds, but the "pain points" and the consequences of design engineering are often "too far over the horizon” for executives.

“Therefore, most of the support for SPDM ventures generally comes from engineering teams, and the simulation teams in particular. It doesn’t help that SPDM is difficult to implement—as difficult, if not more, than PDM. All in all, this is the reason I can see behind the slow growth in SPDM.”

Again, the situation is not encouraging. 

"The real adoption rate within mainstream product development activities has been extremely disappointing from a business impact perspective... Unfortunately, the most common form of SPDM in practice today is still the use of personal hard disk storage on the simulation engineer’s desktop or perhaps a shared drive used in common with other members of their immediate organization. Naming and versioning of simulation models and results is haphazard at best and totally inconsistent in the worst cases. This makes the traceability and pedigree of simulation models and results extremely difficult, if not impossible, to accomplish and can lead to a lack of confidence in the accuracy of the simulation results versus physical test data," CIMdata writes in the 2018 release of its Simulation & Analysis Market Analysis Report.

Nevertheless, thereare some positive signs which point to a possibly larger utilization. 

“The real value of SPDM from a democratization perspective is that, after all, there are tools that enable experts to package the knowledge that can be linked to a design model in a way that makes it possible for many designers without advanced simulation knowledge to take part of, and even do, simulations,” says Halpern.

Turning Months into Days

One company that has SPDM platforms to its advantage is Boeing. By tying together simulation and process data, Boeing manages to shorten some development processes substantially.

This goes well in line with other cases where development processes have been shortened from months to days. In extreme cases—when the correct knowledge, interpretation and the correct simulation results are all embedded in the design model—the development process can be shortened to hours.

This proves SPDM solutions can be a key to success when the use of simulation tools is constantly growing—with the caveat that they are not only used in “normal" design processes, but also in later phases: during the product realization process, as well as when products are in use. 

More and more PLM vendors are also starting to look at packaging and developing solutions that make simulation more accessible to multiple stakeholders in product development teams. It’s common knowledge that there is a gap and that the demand for bridging the gap is on the rise. Sweden-based multiphysics software vendor, COMSOL (with the Application Builder), was early to offer solutions for this, but also the simulation giant ANSYS, MSC and the three PLM majors (Siemens PLM, Dassault and PTC) are now working on broadening their respective platforms’ functionalities related to SPDM. The PLM rocket, Aras, closed the gap between simulation and developmentwhen it acquired Comet Solutions at the end of September 2018.

“Much remains to be gained if we can close the gap between simulation and mainstream design by giving simulation analysts the opportunity to repeat and reuse simulations while connecting the analysis to product configuration and multidisciplinary design through quality of life,” says Marc Lind, senior vice president of Strategy at Aras.

SPDM challenges. The adoption of SPDM solutions is far from a question of technology only. People, processes and company culture, as well as governance play significant roles.

SPDM challenges. The adoption of SPDM solutions is far from a question of technology only. People, processes and company culture, as well as governance play significant roles.

SPDM to Understand Product Realization Process

As for the commercial SPDM solutions, CIMdata points at a problem in this context: they have been developed specifically for 3D modeling and simulation (such as finite element analysis and computational fluid dynamics). This means that they often lack effective support for models and information created in 0D/1D systems modeling, which is critical when implementing an MBSE (Model-Based Systems Engineering) approach. 

However, the major solution providers are now recognizing this need and the analyst expects to see significant progress in this area over the next several years.

But the low mainstream adoption rate is far from a question of technology alone. People, processes and company culture, as well as governance, play significant roles: 

  • People because they are probably the most challenging parts of putting SPDM to effective work in the broader team environment. Organization, education, training, competence, and methodology are critical aspects here  
  • Processes because they, among other things, have to address areas like PLM integration, S&A best practices, roadmap navigation models, and synchronization between virtual and physical verification and validation
  • Company culture and governance because you have to formulate and carry out a vision, a strategy, and a detailed plan on the path to implementing the SPDM system. 
  • However, software vendors are still in the early days in developing SPDM solutions that are both robust and easy to use. 

    Most analysts alsoagreethat the exponential growth of CAE and the explosion of simulation-related data appearing from increasing digitization, new technologies and disruptive product realization methods requires more competent management systems.

    “Without good SPDM tools, it will be difficult to effectively understand this part of the product realization process,” says Marc Halpern.

    Simulation is an indispensable element throughout this process. Why?

  • Distributed product development and manufacturing is growing stronger
  • Realizing business benefits of model-based system technology (MBSE) is becoming increasingly important as systems of systems become more common
  • Operation of digital twins
  • The creation and utilization of IoT, IIoT and Industry 4.0 concepts has taken off worldwide
  • The increase in the number of additively manufactured parts and components (3D printing) requires new design methodology and new insights
  • Hybrid additive technology (adding material) and subtractive (removing material, i.e. CAM/NC) technologies
  • An increased use of generative design (where the software proposes an optimized design based on the basic model).
  • “SPDM platforms will be crucial to realizing the true potential of PLM, digital threads and digital twins, and enable collaborations with other corporate platforms, such as ERP, MES and MRO to realize Industry 4.0 concepts in the next step,” Halpern adds. 

    CIMdata agrees in its 2018 report: "Companies need to be better at managing simulation models, results and related design information, improving collaboration and reusing and better integrating simulation activities into the PLM environment. Doing this supports a larger audience of product development engineers, engineering managers, product managers and others in the extended organization and supply chain who can benefit from access to simulation information to make more informed decisions."

    Halpern concurs, adding, “But there are also elements in the data management, which I observed in my research on digital twins, which applies to SPDM. I see a strong connection between the digital twin concept and SPDM.”Embedded Knowledge, Disrupting Institutional Silos

    CAE is traditionally one of the more well-preserved siloes in product development. But in recent years, we have seen increased communication between the analysis, simulation and the rest of the members of the product development team. Also, it is clear that new disruptive technology can be a catalyst and is able to break up isolated data structures.

    But there’s more. Can a software developer create solutions that can meet the new requirements to extend collaboration opportunities, Halpern wonders.

    Withoutuncertainty. Is it possible to parameterize the thermal analysis of a microprocessor on a circuit board, so that it can be applied to similar configurations and variations without uncertainties about the mesh?

    Without uncertainty. Is it possible to parameterize the thermal analysis of a microprocessor on a circuit board, so that it can be applied to similar configurations and variations without uncertainties about the mesh?

    During a NAFEM presentation, the Gartner analyst said that this is an example of a capability that one can embed in a model.

    “Some call it encapsulation,” Halpern continued. "But whatever you call it, this kind of encapsulated information can free up engineers from having to be full-time analysts. The specialized terminology, conventions, and features of the simulations can stay under the hood and the interface made considerably easier to use. A complex problem can be solved with a handful of parameters. This would provide simulation to not only engineers, but also to others involved in the product and its design.”

    Aras Takes a Step with Comet Acquisition

    Allowing more engineers to perform simulation is exactly what the PLM developer Aras was aiming for when it purchased Comet. The acquisition is an important step on a roadmap for developing platform-based SPDM to support increased use of simulation for complex scenarios.

    Aras aims to improve Innovator’s ability to handle simulation data. With Comet's technologies, manufacturers and product developers can reuse complex simulations to scale up or down the application and widen the use of simulation results. One result: it is now possible to connect simulations and gain access to experts in the field by offering traceability, access and reuse during the product life cycle.

    Comet's products are largely based on a series of customer-developed and web-implementable "SimApps," with built-in expert knowledge and methods. “These SimApps,” says Aras Marc Lind, “create a simulation-driven design that fits all users, from CAE experts to design engineers. "

    We ask Halpern if this is what he meant by encapsulated knowledge.

    “Exactly!” says the Gartner analyst. “This distinguishes what Aras sells from what I usually see in terms of SPDM technology.”

    He added that Comet's real value in democratizing simulation is its ability to integrate functionality and knowledge into CAD models so that the person making the simulation or evaluation need not worry about complex problems and intricate trade-offs to make the simulations.

    “Encapsulated knowledge takes care of it."

    Web-based simulation a la Aras. Comet’s SimApps (now part of Aras) are web-based simulation programs that areeasy to use, even for salespeople. Product engineerscan perform complex simulations safely. These SimApps can answer specific questions about the design of a product in a productfamily, for example. Comet experts, partners and customers have built, tested, and deployed a comprehensive library of SimApps that capture and execute best practices for simulation, automate repetitive and tedious tasks and secure the power of sophisticated CAE analysis in the hands of both experts and non-expert users.

    Web-based Simulation a la Aras. Comet’s SimApps (now part of Aras) are web-based simulation programs that are easy to use, even for salespeople. Product engineers can perform complex simulations safely. These SimApps can answer specific questions about the design of a product in a product family, for example. Comet experts, partners and customers have built, tested, and deployed a comprehensive library of SimApps that capture and execute best practices for simulation, automate repetitive and tedious tasks and secure the power of sophisticated CAE analysis in the hands of both experts and non-expert users.

    Links Between Users and Non-Experts

    An important point to get SPDM to work is to apply a "vendor-agnostic" implementation by connecting a wide range of CAD, FEA, meshing, 0D/1D simulation tools and proprietary applications. It is a requirement for supporting the often heterogeneous software environments found in organizations.

    Aras's chief architect, Rob McAveney, argues that wider use of simulation has generally deteriorated as the simulation process and data management tools (SPDM) lack effective links between simulation users and the extended enterprise.

    “Expanding the digital thread to include simulation tools and processes has emerged as an important factor for future business models,” he says. “Simulation can add significant value to product development, manufacturing and field operations, but has not yet reached its potential due to limited connection to the rest of the company. Through Comet we can capture what is needed to realize the potential: Repeatability, reusability and traceability for simulation across the entire product life cycle”

    McAveney sees a market growing exponentially, while progressing as the utilization of physical testing decreases. He also points out that the complexity that comes with smartly connected product design and MBSE are important trends that will support the need for this type of platform.

    “We see simulation in its context, with overall system technology processes together with configuration and change, variants, requirements, validation testing and more. The fact that simulation management is often completely disconnected from mainstream processes is a problem as there is no traceability throughout the product life-cycle loop,” says McAveney.

    McAveny points to the importance of developing the "digital thread" and solutions with digital twins for predictive maintenance.

    "With Comet technology we close the gap between simulation and mainstream design by giving simulation analysts methods to repeat and reuse simulation, link the analysis to product configuration and design during the product life cycle,” he summarizes.

    He also points to Comet's ability to handle mixed models, different data types and representations of the same product. The same applies to assembly, which also needs to be simulated. All in all, this offers "an important aspect of managing system simulations across several technical disciplines."

    The ability to extract intelligence from simulation models and results, rather than just managing data at file level, is also a big advantage over other SPDM systems on the market.

    What the general setup of ANSYS’s SPDM solution EKM looks like.

    What the general setupof ANSYS’s SPDM solution EKM looks like.

    Others Get into the Act

    Aras is not alone. PLM market leaders Siemens and Dassault Systèmes have invested heavily to beef up their simulation solutions in recent years. ANSYS, PTC, MSC, and others, are working on their own SPDM solutions. 

    One of the main reasons for this is the demand from customers in industrial segments that are convinced of the power of simulation and SPDM, such as automotive and aerospace."Among those who are early on to pick up SPDM (like BMW), design decisions --or simulations that led to a design decision - must be traceable," says Marc Halpern. “The test data management functions that Aras is developing with BMW will be interesting to follow. The combination of SPDM with next generation test data management can lead to exciting insights into system development that are designed or evaluated.”

    Will an SPDM solution help them in their efforts? Given the above arguments, it is not unreasonable to expect some kind of difference. But, selling this type platform of is not an easy task.

    In addition, one should bear in mind the built-in structural resistance in corporate organizations, where the simulation has always been its own department and the argument for a well-functioning SPDM encounters is countered with the significant costs of its implementation, especially true at large automotive and aerospace companies.

    But for the bottom line, the return on investment of SPDM looks convincing enough. Even “compelling”, asserts CIMdata in its 2018 report.

    Finally, Aras this week announced a partnership with Visual Collaboration Technologies (VCollab) for simulation visualization, post processing, and reporting. Aras will use the VCollab technology in SPDM processes across the lifecycle. Worth noting is the fact that VCollab can handle formats from all of the big simulation developers (ANSYS, MSC, etc.), which makes it easier to spread and understand simulation results in broader product realization teams. This is one of the greatest values with SPDM.


    Indian Bank Recruitment 2018: Apply online for 145 Specialist Officer posts | killexams.com real questions and Pass4sure dumps

    NEW DELHI: The Indian Bank, a leading Public Sector Bank, has invited applications for the Specialist Officer SO Posts of Assistant General Manager, Assistant Manager, Manager, Senior Manager, & Other Posts.

    The eligible candidates can apply online through its official website indianbank.in from April 10, 2018 to May 2, 2018.

    Direct link to apply online: http://www.indianbank.in/career.php

    NotificationEnglish: http://www.indianbank.in/pdfs/SOENG.pdf

    Hindi: http://www.indianbank.in/pdfs/SOHIN.pdf

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    Important DatesStarting Date to Apply Online: April 10, 2018Closing Date to Apply Online: May 2, 2018Last date for submission of Application Fee: May 2, 2018

    Vacancy Details

    Positions in Information Technology Department / Digital Banking Department

    Post Code Post Role / Domain Scale Vacancy 1 Assistant General Manager System Administrator - AIX, HP-UX, Linux, Windows V 1 2 Chief Manager DBA - Oracle, MySQL, SQL-Server, DB2 IV 2 3 Manager DBA - Oracle, MySQL, SQL-Server, DB2 II 2 4 Chief Manager System Administrator - AIX, HP-UX, Linux, Windows IV 1 5 Manager System Administrator - AIX, HP-UX, Linux, Windows II 2 6 Senior Manager Middleware Administrator - Weblogic, Websphere,JBOSS, Tomcat, Apache, IIS. III 2 7 Chief Manager Application Architect IV 1 8 Manager Application Architect II 1 9 Chief Manager Big Data, Analytics, CRM IV 1 10 Senior Manager Big Data, Analytics, CRM III 1 11 Chief Manager IT Security Specialist IV 1 12 Manager IT Security Specialist II 2 13 Chief Manager Software Testing Specialist IV 1 14 Manager Software Testing Specialist II 2 15 Chief Manager Network Specialist IV 1 16 Senior Manager Network Specialist III 1 17 Manager Virtualisation specialist for VMware, Microsofthypervisor, RHEL(Red Hat Enterprise Linux) II 2 18 Senior Manager Project architect III 1 19 Senior Manager Data Centre Management III 1 20 Manager Network administrator II 2 21 Chief Manager Cyber security specialist IV 1 22 Senior Manager Cyber security specialist III 2 Total 31 Positions in Information Systems Security Cell Post Code Post Role / Domain Scale Vacancy 23 Senior Manager Senior Information Security Manager III 1 24 Manager Information Security Administrators II 3 25 Manager Cyber Forensic Analyst II 1 26 Manager Certified Ethical Hacker &Penetration Tester II 1 27 Assistant Manager Application Security Tester I 1 Total 7 Positions in Treasury Department Post Code Post Role / Domain Scale Vacancy 28 Senior Manager Regulatory Compliance III 1 29 Senior Manager Research Analyst III 1 30 Senior Manager Fixed Income Dealer III 2 31 Manager Equity Dealer II 1 32 Senior Manager Forex Derivative Dealer III 1 33 Senior Manager Forex Global Markets Dealer III 1 34 Manager Forex Dealer II 1 35 Senior Manager Relationship Manager - Trade Finance and Forex III 3 36 Senior Manager Business Research Analyst - Trade Finance and Forex III 1 37 Senior Manager Credit Analyst - Corporates III 1 Total 13 Position in Security Department Post Code Post Role / Domain Scale Vacancy 40 Manager Security Officer II 25 Positions in Credit Post Code Post Role / Domain Scale Vacancy 41 Senior Manager Credit III 20 42 Manager Credit II 30 Total 50 Positions in Planning and Development Department Post Code Post Role / Domain Scale Vacancy 43 Manager Statistician II 1 44 Assistant Manager Statistician I 1 Total 2 Positions in Premises and Expenditure Department Post Code Post Role / Domain Scale Vacancy 45 Manager Electrical II 2 46 Manager Civil II 2 47 Assistant Manager Civil I 6 48 Assistant Manager Architect I 1 Total 11 RESERVATION SCALE TOTAL SC ST OBC UR OC VI HI ID V 1 0 0 0 1 0 0 0 0 IV 9 2 0 2 5 0 0 0 0 III 42 6 3 11 22 1 0 1 0 II 84 12 6 22 44 0 1 1 1 I 9 1 0 2 6 1 0 0 0 PAY SCALE AND EMOLUMENTS Scale I 23700 980 30560 1145 32850 1310 42020 Scale II 31705 1145 32850 1310 45950 Scale III 42020 1310 48570 1460 51490 Scale IV 50030 1460 55870 1650 59170 Scale V 59170 1650 62470 1800 66070

    Age Limit (as on January 1, 2018)

    Post Age Limit Assistant General Manager 30 to 45 years Manager (All Other) 23 to 35 years Manager (Equity Dealer, Forex Dealer, Risk Management, Security Officer, Credit, Statistician) 25 to 35 years Senior Manager (All Other) 25 to 38 years Senior Manager (Regulatory Compliance, Research Analyst, Fixed Income Dealer, Forex Derivative Dealer, Forex Global Markets Dealer, Relationship Manager - Trade Finance and Forex, Business Research Analyst - Trade Finance and Forex,Risk Management) 27 to 38 years Chief Manager 27 to 40 years Assistant Manager 20 to 30 years

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    Post Code Additional Qualification Experience 1 Professional level certification inSystem Administration 10 years Experience in maintenance and Administration of Operating Systems, Databases, Backup Management and Data Centre Management 2 Professional level certification in Database Administration 7 years Experience in maintenance and administration of databases likeOracle/ DB2/ MySql/ SQL Server 3 Associate level certification inDatabase Administration. 3 years Experience in maintenance and administration of databases likeOracle/ DB2/ MySql/ SQL Server. 4 Professional level certification in System Administration 7 years Experience in maintenance andAdministration of Operating Systems. 5 Associate level certification inSystem Administration 3 years Experience in maintenance and Administration of Operating Systems 6 Certification in Middleware Solution 5 years Experience in maintenance andAdministration of Middleware. 7 Certification in Software Development & Programming 7 years Experience in application design, code review and Documentation 8 Certification in Software Development& Programming 7 years Experience in application design, code review and Documentation 9 Certification in Big Data/Analytics/ CRM solution 7 years Experience in Analyzing data, uncover information, derive insights and implement data-driven strategies and datamodels in Big Data/ Analytic/ CRM technology 10 Certification in Big Data/Analytics/ CRM solution 3 years Experience in Analyzing data, uncover information, derive insights and implement data-driven strategies and data models in Big Data/Analytic/ CRM technology 11 Certified Information Security Manager/ Certified Information Systems Security Professional 7 years Experience in implementing security improvements by auditing and assessing the current situation; evaluating trends; anticipating requirements and making relevant configuration/strategychanges to keep the organization secure. 12 Checkpoint Certified SecurityExpert /CISCO Certified Security Professional. 3 years Experience in implementing security improvements by assessing the current situation; evaluating trends; anticipating requirements and makingchanges to keep the organization secure 13 Certification in software testing. Experience in Software Testing 14 Certification in software testing. Experience in Software Testing 15 Cisco Certified Internetwork Expert (Switching and Routing). 7 years Experience in Routing and switching. Design and implementation of WAN networks. Experience (a) in routing using Border Gateway Protocol(BGP). (b) Drawing up specifications for procurement of Network devices includingrouters, switches, firewalls 16 Cisco Certified InternetworkExpert (Switching and Routing). 5 years Experience in Routing and switching. Design and implementation of WAN networks. Experience in implementation of NetworkAdmission Control (NAC) 17 Associate level CertificationVirtualization Technology. 3 years Experience in Administrationof systems in Virtualized environment 18 Nil 5 years Experience in conceptualizing, esigning and implementation of High-valueorganization level IT projects 19 It is desirable to have certificationin Data Centre Management. 5 years Experience in Managing DataCentre Operations. 20 Cisco Certified NetworkProfessional (Routing and Switching) 3 years Experience in Network Troubleshooting,Network Protocols, Routers, Network Administration. 21 Certification in Cyber Security froma recognized institution 7 years Experience Managing Cyber SecurityOperation Centre. 22 Certification in Cyber Security froma recognized institution 5 years Experience Managing Cyber SecurityOperation Centre HOW TO APPLY ONLINE
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  • Power Issues Rising For New Applications | killexams.com real questions and Pass4sure dumps

    Managing power in chips is becoming more difficult across a wide range of applications and process nodes, forcing chipmakers and systems companies to rethink their power strategies and address problems much earlier than in the past.

    While power has long been a major focus in the mobile space, power-related issues now are spreading well beyond phones and laptop computers. There are several reasons for this:

  • Power dissipation is becoming increasingly difficult in the finFET world, a problem that is made worse by the fact that at each new node after 16/14nm leakage current and dynamic power density are both increasing.
  • New applications such as AI and deep learning require massive compute power, and new architectures depend on rapid throughput and raw performance. But they also rely on keeping all of the processing elements in a chip busy at all times, which creates power dissipation problems.
  • More customization is required to tackle new markets. As a result, there are fewer derivative chips and more one-off designs, so problems detected and solved for one chip may be significantly different than problems detected in other chips and much more expensive to fix.
  • These challenges extend from data centers, where AI, networking, and telecommunications require massive amounts of energy, all the way to the edge. At 7nm, it’s not uncommon for chips to be large, sometimes at reticle size, with hundreds or thousands of processor cores. But unlike in the past, where those processors were mostly dark except for required bursts of activity, some of the new application areas require more of these processing elements to be on more often, if not all the time.

    And this is where problems such as heat, electromigration, power-related noise and reliability become particularly difficult to manage.

    “CPU Utilization, power management and device reliability must be tightly and accurately thermally managed on die,” said Stephen Crosher, CEO of Moortec. “Otherwise, data center electricity bills can be millions of dollars higher than necessary each year. Datacenter operators are now seeing the direct correlation between site-running costs and the thermal monitoring and management adopted way down deep within the system at chip level.”

    This is driving new techniques such as real-time, in-chip thermal guard-banding to enhance the implementation of health monitoring, failure prediction and the design of higher rack density configurations. But in many cases the solutions are just barely keeping pace with the problems. Everyone wants to utilize AI/ML/DL in a chip, whether those chips are used inside data centers or at the edge, but the multiply/accumulate processing consumes a lot of energy.

    “Whether you’re doing that to a specialized CNN block, as in the case of embedded vision processes, or whether you’re doing it in a graphics chip with GPUs, it’s all about multiply accumulates,” said Yudhan Rajoo, technical marketing manager for foundation IP at Synopsys. “The way we deal with this problem is primarily after the RTL has been written, by instantiating certain complex cells in the RTL by the designer in a hand-placed fashion. For example, there are large boot multiplexers — large compressors and 16-bit muxes and multipliers that we are starting to add in to reduce the overall size of the design. That reduces the number of routes that you need to make, and as you go down in nodes this reduction in number of routes saves a lot of switching power. These things are continuously running and transmitting signals, so as little connection as you can make is what really helps save power.”

    These decisions start up front during the planning phase of the design. But as with any other type of design, engineering teams are very worried about design timelines and tapeout timelines, and power can have a big impact on schedules.

    “There’s a big race to come up with the best neural network processing architecture, and these RTLs keep on changing until pretty much the last month of tapeout,” Rajoo said. “As a result, design teams are very worried about finding [library] solutions that give enough flexibility to modify things down the line. This has risen as a prime consideration for both SoC designers and their design managers who want to have this flexibility. These teams need a breadth of options, especially on advanced nodes, because the number of foundries that are doing the most advanced nodes is down to two, maybe three if you’re being generous.”

    Within these new architectures, optimization around power is becoming a critical design element. “Low-power design is not limited to platforms like mobile or IoT,” said Dave Pursley, senior principal product manager for the Digital & Signoff Group at Cadence. “Computationally intensive algorithms are an interesting problem because the computations themselves will require a significant amount of energy to perform. In other words, there is a fairly high ‘floor’ when it comes to the amount of energy that will be consumed.”

    All of this has pushed the design space well beyond just the hardware to the movement of data through a system, including what gets processed where, how precise the computation needs to be, and how it is stored and read in memory.

    “Theoretically, from a dynamic switching perspective, the lowest energy solution to compute an algorithm would be to compute it as in as few clock cycles as possible and then shut off via clock gating—or better yet, via power shutoff,” Pursley said. “That minimizes the amount of ‘unproductive’ switching, such as muxing, flip-flops, and the amount clock-switching but that often is not the best tradeoff, because the required silicon area would be larger. That, in turn, increases costs, leakage, and even dynamic energy due to the higher capacitance of longer interconnects. Moreover, it may not even be feasible, especially for computationally intensive algorithms. Power is energy over time, so computing an energy-hungry algorithm in a short time may be infeasible or too costly from a power perspective.”

    In these cases, it is the task of the designer and the EDA tools they use to amortize that energy over time. The goal is an acceptable power profile with minimal energy overhead, while still meeting the performance requirements of the application. So while RTL and physical optimizations can reduce power by 20% or more, the most important optimization begins with a power-efficient RTL architecture. That includes an understanding of the clock speeds of the various blocks, how they communicate with each other, what is the memory architecture and the throughput, and what is the overall power impact of the architecture. Modeling all of this remains difficult, however, largely because so many of the applications and architectures are new.

    “With finFETs, with self-heating behavior, we have some history from the earliest finFETs,” said João Geada, chief technologist for the semiconductor business unit at ANSYS. “This is the part that concerns me the most. We are making parts for which we don’t really have history on the modeling side on the foundry. We have the simulation technology. If we have the models — both on the highly detailed stuff, as well as on the large-scale chip-wide stuff on our side. We do need both, but we depend critically on models, and that’s still a very challenging area.”

    Still, the power problem is so large and diffuse that some higher level of abstraction is required.

    “In many cases, the best way to figure this out is to use high-level synthesis (HLS) to actually create multiple RTLs with different architectures and actually measure the power with realistic stimulus,” Pursley said, noting that state-of-the-art RTL power estimation tools today can produce power estimates within 15% of sign-off. “The real trick is to ensure you have realistic stimulus for measuring power. For example, for a processor the ‘boot Linux’ test is great for functional testing and peak power analysis, but it is likely a terrible metric for optimizing average power to maximize battery life. A better stimulus would be the processor running its typical applications. It is important to use the correct stimuli, or windows of stimuli, for the correct optimization tasks. Otherwise, you or your tools will be making optimization decisions based on bad data.”

    If the stimulus is known to be representative, it can also feed into the implementation tools to ensure that the same power goals and tradeoffs are being made throughout the flow. Introducing or changing stimuli late in the flow increases the chance of a non-convergent optimization flow, or at least one that takes longer to converge.

    Then, as early as RTL synthesis, multi-mode, multi-corner (MMMC) optimization should be used, he said. That allows RTL physical synthesis tools to create power-optimized netlists, which include well-balanced logic to avoid glitching, optimal leakage optimization, advanced clock gating, multi-bit cell inferencing, and power-aware design-for-test.

    “Like the architectural optimizations, these types of implementation optimizations have the most impact on power when introduced early in the flow,” Pursley said. “Introducing MMMC in layout or signoff changes the optimization goals partway through the flow. At best, this means that optimizations done by RTL synthesis were wasted and may be undone. At worst, you now have a flow that will take many iterations to converge through signoff, with an increased chance of a costly re-spin due to error-prone manual iterations.”

    Methods for reducing power at RTL and below — power gating, clock gating, multi-Vdd, multi-threshold, DVFS — are well understood. The problem is that by the time RTL is available, the project is already well advanced and it’s too late to make any bigger changes, said Tim Kogel, principal applications engineer at Synopsys.

    The biggest impact on power, energy, heat, and cost is achieved at the system level, and it works best when the design team has detailed knowledge of the end application and use cases. That allows engineers to group components into power domains that can be powered down as much as possible, as well as to define power management policy and operating points for DVFS. It also helps to figure out the best way to distribute workloads to processing and memory resources to stay within power and thermal budgets.

    “The power needs to be considered and optimized well before RTL availability, at the architecture specification phase,” said Kogel. “The problem is that accurate data about the power consumption is typically not available during architecture specification phase. At best you have some data-sheet numbers and data from previous projects. It becomes worse when you try to roll up that premature data in spreadsheets because you are missing the dynamic effect of the application utilizing different components at different points in time. Even if the hardware implementation has been designed for low power, the effective power consumption is often much higher than expected because the software does not leverage the low-power mechanism provided by the hardware. Thus, a small oversight from the software developer can prevent a power domain from being shut down.”

    To enable early power estimation, IEEE 1801 UPF has defined a standard format for system level power models. “This way UPF power monitors can be added to architecture models and virtual platforms for software development,” Kogel said. “Architects can analyze and optimize power based on the actual activity, and software developers become aware of the impact of their software on power consumption. Even if the power data is not accurate, trend-based analysis based on the simulated activity provides valuable insight. Later the initial power data can be refined as more accurate measurements become available.”

    While characterization of system-level power models remain a challenge, it’s possible power characterization tools could be enhanced to generate system-level power models.

    Power matters moreThere has never been a more pressing need to care about the power in chips as today because of the rapid rise in data generated by the proliferation of connected sensors and devices.

    “In the days of PCs where the source of power supply used to be 220V AC, it was all fine,” said Mohammed Fahad, product specialist at Mentor, a Siemens Business. “But with the advent of handheld devices like smart phones and tablets, it’s not just that the geometries of the computing devices have shrunk. The devices are getting loaded with more and more apps and services. Possibilities to fabricate chips at smaller nodes have enabled the chipmakers to pack billions of transistors on even smaller silicon real-estates. With enormously complex logic going into even tinier chips, the power consumption is getting on the critical path and often causing chips to burn out. Industry research has found that power is the second most frequent reason for chip re-spins. Billions of dollars in investment are going down the drain. This is why design companies today have a very robust low power methodologies in place, built around sophisticated power estimation and optimization tools.”

    Performing power estimation is about knowing the power scenario of the chip. Designers would like to understand the overall power consumption of their blocks, where the hotspots are, and which areas are overshooting the budget. In other words, where is power being wasted? If power consumption of the chip stays within the budget, it’s all good news. But what if it doesn’t?

    Fahad noted that RTL power estimation tools define a problem statement for the RTL power optimization tools to address it, identify the computational redundancies in RTL, and inform the user how these redundancies in the code could be eliminated. Tools also provide ways to automatically fix these redundancies and write out the power-optimized RTL. “Optimizing the RTL for power early in the design stages pays higher dividends than engaging later in the cycle. Therefore, low-power methodology demands that power optimization should be run well before the code freeze so that it is easy to make any power-saving code changes at the RTL or architectural level-if necessary.”

    There are various ways in which a chip’s power consumption can be reduced or controlled, including gating the non-observable operations on flops and memories, stopping the design toggles for stable inputs and outputs and bypassing the stable memory accesses. At the architecture level, changing the shift register operations to circular buffer, and finding a common gating condition for blocks rather than just flops also can help.

    Fundamentally, the key to effective power management, from the smallest battery-operated IoT devices to the hungriest GPU and SoC designs, is drawing only the power that is really needed. Different functions on a chip should run at the lowest voltage and clock speed that can deliver the required performance, while functions not currently in use should be on standby or turned off entirely. To accomplish this, complex chips have dozens or even hundreds of power domains, each of which controls the operating state for a portion of the design.

    The rules for how these domains can be manipulated are usually quite complex, and iterating through all possible legal power combinations in simulation is impractical. One solution to finding and fixing potential problems may require applying existing tools in new ways.

    “Rules for which power domains should be on or off depending on what the chip is doing can be captured in the form of assertions,” said Tom Anderson, technical marketing consultant at OneSpin Solutions, noting that formal can prove that only legal combinations of power domain settings are possible, or generate tests showing violations if there are bugs in the design. “Formal verification can prove that these rules are satisfied under all conditions or report bugs. Finding and fixing power-related issues pre-silicon is critical to avoid a chip that doesn’t work because key functions are powered down, or one that suffers thermal breakdown when too much of the chip is turned on at the same time.”

    For this, power estimation isn’t enough. “It’s not that we shouldn’t do anything at the RTL,” said Madgy Abadir, vice president of marketing at Helic. “You can run some RTL power estimation and do things like that, but it is not sufficient. Anything you can do to improve on your design at the RTL is always a plus, but it’s not going to be the full answer. Especially at the physical level, there are phenomena such as thermal and electromagnetic effects, and these effects can only be seen once the layout is complete. Once you have the actual physics, such as the IR drop, analysis needs to happen on the real physical layout that you are planning to implement. Only when you see the effects can you decide if it is acceptable or not. This is not something that can be characterized early on and just put it in a library.”

    Especially for high-power-consuming chips like GPUs, a lot depends on the application that is running.

    “When people develop GPUs, it’s like developing a microprocessor in the old days,” Abadir said. “They don’t know exactly what applications people will be running, and it is general-purpose. There might be many, many customers and applications that would change over time. It may take a couple of years for that to get developed from the time it’s in RTL to the time it is on the shelf. During that time a lot of software gets written, a lot of apps will be developed. The algorithms are where the optimization needs to happen, and some of it depends on what type of algorithm you need to be running. If you’re doing pattern matching or if you’re doing sorting or searching, there are many different ways of executing these types of tasks. Every one of them has a different power, a different performance kind of characteristic. Depending on what you’re trying to do and how good your software developers are, at the end of the day, this is what determines the actual power consumption of the task.”

    This is where knowledge of the end application really helps. “If I am developing a GPU and have knowledge of the type of application that would run on my chip eventually, which in a lot of cases people do, they try to do performance modeling and power modeling in the early stages to figure out the architecture — which type and what to do,” he said. “When it comes to power, it’s a very difficult problem. The problem is how to estimate power at the high level. Some approach this from a characterization point of view, which means you characterize gates and cells, the worst case for timing and for power. But in many cases, such as with GPUs, we’re doing things that have not been done before. Where do you get the models? We’re estimating at the high level how much power is required, and this can be a guessing game because it’s not accurate and can be way off from what happens with the real chips. This is because the actual power consumption has to do with the actual physical attributes of the chip.”

    Another significant factor is the choice of algorithm. There may be several different sorting algorithms, for example, each of which may run at a different speed or have different memory requirements. The tradeoffs here can have a big impact on how much power is used, though.

    “As a developer of the chip, at the RTL what do I do? I developed the GPU that can add and multiply, go through memory and get things to operate in parallel, have multiple threads,” Abadir said. “Most of the techniques for lowering the power come in the implementation stage for these type of chips, so doing it early requires control of the application. I need to control the algorithm. ‘Early’ means the keys are in the hands of the software people. ‘Later’ means the keys are in the hands of the hardware people. It might be both of them operating in hardware-software co-design, but later on somebody will pick the algorithm, and now the hardware guy needs to tweak all the possible things that are clock gating.”

    ConclusionThe semiconductor industry is coming to grips with the fact that general-purpose chips are no longer the path forward. The new currency is data, and processing that data quickly with blazing fast throughput and access to memory are key design elements.

    But making this happen without burning up a chip is a massive and growing challenge, and it’s only getting harder as the volume of data increases and the benefits of device scaling decrease. Power is the main gating factor, and it’s becoming much more difficult to fix as compute architectures and demand for processing continue to rise.

    Related Stories

    Power Modeling And Analysis

    Taming NBTI To Improve Device Reliability

    Designing For Ultra-Low-Power IoT Devices



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    weSRCH : https://www.wesrch.com/business/prpdfBU1HWO000SDAL
    Issu : https://issuu.com/trutrainers/docs/e20-385
    Dropmark-Text : http://killexams.dropmark.com/367904/12049372
    Youtube : https://youtu.be/u5B9BxyH4UI
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    publitas.com : https://view.publitas.com/trutrainers-inc/e20-385-pdfpass4sure-e20-385-dumps-and-practice-tests-with-real-questions
    coursehero.com : "Excel"
    Google+ : https://plus.google.com/112153555852933435691/posts/TTtcQiuKBvr?hl=en
    Calameo : http://en.calameo.com/books/00492352644d723ebb55d
    zoho.com : https://docs.zoho.com/file/4yfsm0ded9d0501c44316aaa84369400060fd
    Box.net : https://app.box.com/s/k5udj0u6fwq54vjc9hfmthh9fpthadom






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